Invention Grant
- Patent Title: Via-node-based electromigration rule-check methodology
- Patent Title (中): 基于节点的电迁移规则检查方法
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Application No.: US12041984Application Date: 2008-03-04
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Publication No.: US08438519B2Publication Date: 2013-05-07
- Inventor: Young-Joon Park
- Applicant: Young-Joon Park
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A.R. Cooper; Wade J. Brady III; Frederick J. Telecky, Jr
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.
Public/Granted literature
- US20090228856A1 VIA-NODE-BASED ELECTROMIGRATION RULE-CHECK METHODOLOGY Public/Granted day:2009-09-10
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