Invention Grant
US08438512B2 Method and system for implementing efficient locking to facilitate parallel processing of IC designs
有权
实现有效锁定的方法和系统，以促进IC设计的并行处理
- Patent Title: Method and system for implementing efficient locking to facilitate parallel processing of IC designs
- Patent Title (中): 实现有效锁定的方法和系统，以促进IC设计的并行处理
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Application No.: US13221822Application Date: 2011-08-30
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Publication No.: US08438512B2Publication Date: 2013-05-07
- Inventor: David Cross , Eric Nequist
- Applicant: David Cross , Eric Nequist
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
Public/Granted literature
- US20110314432A1 METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS Public/Granted day:2011-12-22
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