Invention Grant
- Patent Title: Memory dies, stacked memories, memory devices and methods
-
Application No.: US12704354Application Date: 2010-02-11
-
Publication No.: US08437163B2Publication Date: 2013-05-07
- Inventor: Takuya Nakanishi , Yutaka Ito
- Applicant: Takuya Nakanishi , Yutaka Ito
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: G11C5/00
- IPC: G11C5/00 ; G11C7/00 ; G11C8/00

Abstract:
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.
Public/Granted literature
- US20110194326A1 MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS Public/Granted day:2011-08-11
Information query