Invention Grant
- Patent Title: Semiconductor device and method of manufacturing a semiconductor device
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US13036490Application Date: 2011-02-28
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Publication No.: US08436451B2Publication Date: 2013-05-07
- Inventor: Hiroshi Yamashita
- Applicant: Hiroshi Yamashita
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2010-041608 20100226
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's.
Public/Granted literature
- US20110210434A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2011-09-01
Information query
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