Invention Grant
- Patent Title: Exposure mask used for manufacturing a semiconductor device having impurity layer and a semiconductor device
- Patent Title (中): 用于制造具有杂质层的半导体器件和半导体器件的曝光掩模
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Application No.: US13049420Application Date: 2011-03-16
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Publication No.: US08436402B2Publication Date: 2013-05-07
- Inventor: Ken Tomita
- Applicant: Ken Tomita
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-066585 20100323
- Main IPC: H01L27/148
- IPC: H01L27/148 ; H01L31/062 ; H01L31/113

Abstract:
An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region.The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
Public/Granted literature
Information query
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