Invention Grant
US08435901B2 Method of selectively etching an insulation stack for a metal interconnect
有权
选择性地蚀刻用于金属互连的绝缘堆叠的方法
- Patent Title: Method of selectively etching an insulation stack for a metal interconnect
- Patent Title (中): 选择性地蚀刻用于金属互连的绝缘堆叠的方法
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Application No.: US12814255Application Date: 2010-06-11
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Publication No.: US08435901B2Publication Date: 2013-05-07
- Inventor: Kelvin Zin
- Applicant: Kelvin Zin
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Wood, Herron & Evans, LLP
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461

Abstract:
A method of patterning an insulation layer is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a cap layer, a SiCOH-containing layer overlying the cap layer, and a hard mask overlying the SiCOH-containing layer. The method further includes transferring a pattern through the film stack by performing a series of etch processes in a plasma etching system, wherein the series of etch processes utilize a temperature controlled substrate holder in the plasma etching system according to a substrate temperature control scheme that achieves etch selectivity between the SiCOH-containing layer and the underlying cap layer.
Public/Granted literature
- US20110306214A1 Method of selectively etching an insulation stack for a metal interconnect Public/Granted day:2011-12-15
Information query
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