A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.