Invention Grant
- Patent Title: Semiconductor memory device
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Application No.: US12889018Application Date: 2010-09-23
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Publication No.: US08418042B2Publication Date: 2013-04-09
- Inventor: Shinichi Kanno
- Applicant: Shinichi Kanno
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-069012 20100324
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.
Public/Granted literature
- US20110239083A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2011-09-29
Information query
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