Invention Grant
US08417864B2 Cascade-able serial bus device with clock and management and cascade methods using the same
有权
具有时钟和管理级联串行总线设备的串级总线设备
- Patent Title: Cascade-able serial bus device with clock and management and cascade methods using the same
- Patent Title (中): 具有时钟和管理级联串行总线设备的串级总线设备
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Application No.: US12761347Application Date: 2010-04-15
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Publication No.: US08417864B2Publication Date: 2013-04-09
- Inventor: Yuan-Heng Sun , Yeu-Horng Shiau
- Applicant: Yuan-Heng Sun , Yeu-Horng Shiau
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Priority: TW98144140A 20091222
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F13/00 ; H05K7/10

Abstract:
A cascade-able serial bus device for coupling between a host device and another serial bus device is disclosed. The host device includes a serial bus interface. The serial bus device includes a first connection interface, a second connection interface and a bypassing module. The first connection interface is coupled to the serial bus interface of the host device. The second connection interface is coupled to the second serial bus device. The bypassing module is coupled to a chip select (CS) signal line of the serial bus interface and the second connection interface for selectively bypassing or non-bypassing the CS signal to the second serial bus device.
Public/Granted literature
- US20110153888A1 CASCADE-ABLE SERIAL BUS DEVICE WITH CLOCK AND MANAGEMENT AND CASCADE METHODS USING THE SAME Public/Granted day:2011-06-23
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