Invention Grant
- Patent Title: SRAM leakage reduction circuit
- Patent Title (中): SRAM漏电还原电路
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Application No.: US13291360Application Date: 2011-11-08
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Publication No.: US08416633B2Publication Date: 2013-04-09
- Inventor: Michael Anthony Zampaglione , Michael Tooher
- Applicant: Michael Anthony Zampaglione , Michael Tooher
- Applicant Address: CA Ottawa
- Assignee: Mosaid Technologies Incorporated
- Current Assignee: Mosaid Technologies Incorporated
- Current Assignee Address: CA Ottawa
- Agent Dennis R. Haszko
- Main IPC: G11C5/14
- IPC: G11C5/14

Abstract:
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.
Public/Granted literature
- US20120057416A1 SRAM LEAKAGE REDUCTION CIRCUIT Public/Granted day:2012-03-08
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