Invention Grant
US08416106B2 Calibration scheme for resolution scaling, power scaling, variable input swing and comparator offset cancellation for flash ADCs
有权
用于闪存ADC的分辨率缩放，功率缩放，可变输入摆幅和比较器偏移消除的校准方案
- Patent Title: Calibration scheme for resolution scaling, power scaling, variable input swing and comparator offset cancellation for flash ADCs
- Patent Title (中): 用于闪存ADC的分辨率缩放，功率缩放，可变输入摆幅和比较器偏移消除的校准方案
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Application No.: US13090501Application Date: 2011-04-20
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Publication No.: US08416106B2Publication Date: 2013-04-09
- Inventor: Pradip Thachile
- Applicant: Pradip Thachile
- Applicant Address: JP Kawasaki-shi
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki-shi
- Agency: Baker Botts L.L.P.
- Main IPC: H03M1/10
- IPC: H03M1/10
Abstract:
In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.
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