Invention Grant
US08416011B2 Circuit and method for generating body bias voltage for an integrated circuit
有权
用于产生集成电路体偏置电压的电路和方法
- Patent Title: Circuit and method for generating body bias voltage for an integrated circuit
- Patent Title (中): 用于产生集成电路体偏置电压的电路和方法
-
Application No.: US12941104Application Date: 2010-11-08
-
Publication No.: US08416011B2Publication Date: 2013-04-09
- Inventor: Srinivas Reddy Chokka , Prasad Sawarkar
- Applicant: Srinivas Reddy Chokka , Prasad Sawarkar
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Mendelsohn, Drucker & Associates, P.C.
- Agent Steve Mendelsohn
- Main IPC: G05F1/575
- IPC: G05F1/575 ; G05F1/585 ; H02M3/10
Abstract:
A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.
Public/Granted literature
- US20120112820A1 CIRCUIT AND METHOD FOR GENERATING BODY BIAS VOLTAGE FOR AN INTEGRATED CIRCUIT Public/Granted day:2012-05-10
Information query
IPC分类:
