Invention Grant
US08413036B2 Pseudorandom binary sequence checker with control circuitry for end-of-test check
有权
具有用于测试结束检查的控制电路的伪随机二进制序列检查器
- Patent Title: Pseudorandom binary sequence checker with control circuitry for end-of-test check
- Patent Title (中): 具有用于测试结束检查的控制电路的伪随机二进制序列检查器
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Application No.: US12324920Application Date: 2008-11-28
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Publication No.: US08413036B2Publication Date: 2013-04-02
- Inventor: Si Ruo Chen , Hao Li , Jin Song Liu , Tao Wang
- Applicant: Si Ruo Chen , Hao Li , Jin Song Liu , Tao Wang
- Applicant Address: US PA Allentown
- Assignee: Agere Systems LLC
- Current Assignee: Agere Systems LLC
- Current Assignee Address: US PA Allentown
- Agency: Ryan, Mason & Lewis, LLP
- Main IPC: G06F7/02
- IPC: G06F7/02 ; G06F11/22 ; G06F17/50 ; H03M13/00

Abstract:
Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.
Public/Granted literature
- US20100138729A1 Pseudorandom binary sequence checker with control circuitry for end-of-test check Public/Granted day:2010-06-03
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