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US08413015B2 Nonvolatile memory controller with scalable pipelined error correction 有权
具有可扩展流水线纠错的非易失性存储器控制器

Nonvolatile memory controller with scalable pipelined error correction
Abstract:
A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.
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