Invention Grant
US08412996B2 Method and device for checking the integrity of a logic signal, in particular a clock signal
有权
用于检查逻辑信号的完整性的方法和装置,特别是时钟信号
- Patent Title: Method and device for checking the integrity of a logic signal, in particular a clock signal
- Patent Title (中): 用于检查逻辑信号的完整性的方法和装置,特别是时钟信号
-
Application No.: US12020812Application Date: 2008-01-28
-
Publication No.: US08412996B2Publication Date: 2013-04-02
- Inventor: Frederic Bancel , Nicolas Berard , Philippe Roquelaure
- Applicant: Frederic Bancel , Nicolas Berard , Philippe Roquelaure
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Agency: Seed IP Law Group PLLC
- Priority: FR0700594 20070129
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06K5/04 ; G11B5/00 ; G11B20/20 ; G11B27/00 ; G01R31/28 ; H03M13/00 ; H04L7/00

Abstract:
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
Public/Granted literature
- US20080208497A1 METHOD AND DEVICE FOR CHECKING THE INTEGRITY OF A LOGIC SIGNAL, IN PARTICULAR A CLOCK SIGNAL Public/Granted day:2008-08-28
Information query