Invention Grant
US08412996B2 Method and device for checking the integrity of a logic signal, in particular a clock signal 有权
用于检查逻辑信号的完整性的方法和装置,特别是时钟信号

Method and device for checking the integrity of a logic signal, in particular a clock signal
Abstract:
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
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