Invention Grant
US08412989B2 Tap time division multiplexing with scan test 有权
抽头时分复用与扫描测试

Tap time division multiplexing with scan test
Abstract:
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
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