Invention Grant
- Patent Title: Leveraging chip variability
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Application No.: US12819100Application Date: 2010-06-18
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Publication No.: US08412882B2Publication Date: 2013-04-02
- Inventor: Benjamin Zorn , Ray Bittner , Darko Kirovski , Karthik Pattabiraman
- Applicant: Benjamin Zorn , Ray Bittner , Darko Kirovski , Karthik Pattabiraman
- Applicant Address: US WA Redmond
- Assignee: Microsoft Corporation
- Current Assignee: Microsoft Corporation
- Current Assignee Address: US WA Redmond
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/02

Abstract:
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
Public/Granted literature
- US20110314210A1 LEVERAGING CHIP VARIABILITY Public/Granted day:2011-12-22
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