Each pixel region includes first and second pixel electrodes (17a, 17b) and first and second capacitor electrodes (67x, 67y) positioned on a layer where a data signal line (15) exists. The first and second capacitor electrodes are aligned in a row direction in such a manner as to overlap a retention capacitor line (18) via a first insulating film and to overlap the second pixel electrode (17b) via a second insulating film. A drain electrode (9) of a transistor (12), the first pixel electrode (17a), a first connection line (38) connected with the first capacitor electrode (67x), and the second connection line connected with the second capacitor electrode (67y) are electrically connected with one another. A part of the first connection line (38) and a part of the second connection line (39) do not overlap the retention capacitor line (18). This allows increasing production yields of an active matrix substrate based on a capacitive coupling pixel division system and a liquid crystal panel including the active matrix substrate.