Invention Grant
- Patent Title: Method of fabricating a deep trench insulated gate bipolar transistor
- Patent Title (中): 制造深沟槽绝缘栅双极晶体管的方法
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Application No.: US13565846Application Date: 2012-08-03
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Publication No.: US08410548B2Publication Date: 2013-04-02
- Inventor: Vijay Parthasarathy , Sujit Banerjee
- Applicant: Vijay Parthasarathy , Sujit Banerjee
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
Public/Granted literature
- US20120313140A1 Method of Fabricating a Deep Trench Insulated Gate Bipolar Transistor Public/Granted day:2012-12-13
Information query
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