Invention Grant
- Patent Title: Techniques and apparatus to validate an integrated circuit design
- Patent Title (中): 验证集成电路设计的技术和设备
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Application No.: US13194916Application Date: 2011-07-30
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Publication No.: US08407643B1Publication Date: 2013-03-26
- Inventor: Sean R. Atsatt
- Applicant: Sean R. Atsatt
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble Carlyle Sandridge & Rice, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Techniques for generating an integrated circuit (IC) design configuration file are provided. The techniques include compiling a design file to generate a compiled IC design. The design file may include multiple constraints that are associated with the design. Status reports are generated based on the compiled IC design and the associated constraints. At least a portion of the generated status reports is encoded. A configuration that includes the encoded portion of the status reports is generated based on the compiled IC design is generated.
Public/Granted literature
- US1293149A Finder attachment for cameras. Public/Granted day:1919-02-04
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