When a reception of a data signal is detected, a power supply control start signal is generated and the data signal is outputted to a signal processor in a fixed time. A power supply control signal for suppressing an output voltage variation of a power supply of the signal processor is generated until a processing completion signal from the signal processor is received after the power supply control start signal is generated. Alternatively, data signals received are separated by type and outputted to respective signal processors. After validity setting signals by type are received, a power supply control start signal is generated when the validity setting signals become valid in an overlapped manner. Such a power supply control signal is generated until one of the validity setting signals which have been valid so far becomes invalid after the power supply control start signal is generated.