Invention Grant
US08407277B1 Full subtractor cell for synthesis of area-efficient subtractor and divider
有权
用于合成区域效率减法器和分频器的完全减法器单元
- Patent Title: Full subtractor cell for synthesis of area-efficient subtractor and divider
- Patent Title (中): 用于合成区域效率减法器和分频器的完全减法器单元
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Application No.: US12258424Application Date: 2008-10-26
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Publication No.: US08407277B1Publication Date: 2013-03-26
- Inventor: Sabyasachi Das
- Applicant: Sabyasachi Das
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Alford Law Group, Inc.
- Agent William E. Alford
- Main IPC: G06F7/50
- IPC: G06F7/50
Abstract:
A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first bit and an inverter output to receive the complemented second bit; and an OR gate having first and second inputs coupled to a first AND gate output and a second AND gate output. An XOR gate output and an OR gate output generate the sum output bit and the carry output bit.
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