Invention Grant
US08406051B2 Iterative demodulation and decoding for multi-page memory architecture
有权
用于多页存储器架构的迭代解调和解码
- Patent Title: Iterative demodulation and decoding for multi-page memory architecture
- Patent Title (中): 用于多页存储器架构的迭代解调和解码
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Application No.: US12781780Application Date: 2010-05-17
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Publication No.: US08406051B2Publication Date: 2013-03-26
- Inventor: Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
- Applicant: Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Hollingsworth Davis, LLC
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.
Public/Granted literature
- US20110280069A1 ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE Public/Granted day:2011-11-17
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