Invention Grant
- Patent Title: Providing a feedback loop in a low latency serial interconnect architecture
- Patent Title (中): 在低延迟串行互连架构中提供反馈回路
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Application No.: US12969249Application Date: 2010-12-15
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Publication No.: US08405533B2Publication Date: 2013-03-26
- Inventor: Ehud Shoor , Dror Lazar , Assaf Benhamou
- Applicant: Ehud Shoor , Dror Lazar , Assaf Benhamou
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H03M9/00
- IPC: H03M9/00
Abstract:
In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
Public/Granted literature
- US08314724B2 Providing a feedback loop in a low latency serial interconnect architecture Public/Granted day:2012-11-20
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