Invention Grant
- Patent Title: Integrated circuit packaging system with stacked configuration and method of manufacture thereof
- Patent Title (中): 具有堆叠结构的集成电路封装系统及其制造方法
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Application No.: US12410983Application Date: 2009-03-25
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Publication No.: US08405197B2Publication Date: 2013-03-26
- Inventor: Jong-Woo Ha , DaeSik Choi , Byoung Wook Jang
- Applicant: Jong-Woo Ha , DaeSik Choi , Byoung Wook Jang
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L21/58
- IPC: H01L21/58 ; H01L23/492
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system.
Public/Granted literature
- US20100244217A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2010-09-30
Information query
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