Invention Grant
- Patent Title: Solder layer and electronic device bonding substrate and submount using the same
- Patent Title (中): 焊接层和电子器件接合基板和使用其的基座
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Application No.: US11694920Application Date: 2007-03-30
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Publication No.: US08404359B2Publication Date: 2013-03-26
- Inventor: Yoshikazu Oshika , Masayuki Nakano
- Applicant: Yoshikazu Oshika , Masayuki Nakano
- Applicant Address: JP Tokyo
- Assignee: Dowa Electronics Materials Co., Ltd.
- Current Assignee: Dowa Electronics Materials Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Chen Yoshimura LLP
- Priority: JP2006-101227 20060331; JP2007-067629 20070315
- Main IPC: B32B5/18
- IPC: B32B5/18 ; B32B15/01 ; B23K1/00

Abstract:
A solder layer and an electronic device bonding substrate using the layer are provided which avoid deteriorating qualities of the electronic device to be bonded. In a solder layer 14 free from lead and formed on a substrate 11 or an electronic device bonding substrate 10 having such a solder layer, the solder layer 14 has a specific resistance of not more than 0.4 Ω·μm. The electronic device bonding substrate 10 can have a thermal resistance of not more than 0.5 K/W and a thickness of not more than 10 μm. Then, voids contained in the solder layer 14 have a maximum diameter of not more than 0.5 μm and the substrate can be a submount substrate.
Public/Granted literature
- US20070228105A1 SOLDER LAYER AND ELECTRONIC DEVICE BONDING SUBSTRATE AND SUBMOUNT USING THE SAME Public/Granted day:2007-10-04
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