A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.