Invention Grant
- Patent Title: Selecting on die test port and off die interface leads
- Patent Title (中): 选择裸片测试端口和离线接口引线
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Application No.: US13370521Application Date: 2012-02-10
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Publication No.: US08402330B2Publication Date: 2013-03-19
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.
Public/Granted literature
- US20120144254A1 INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT Public/Granted day:2012-06-07
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