Invention Grant
US08401140B2 Phase/frequency detector for a phase-locked loop that samples on both rising and falling edges of a reference signal
有权
用于在参考信号的上升沿和下降沿进行采样的锁相环的相位/频率检测器
- Patent Title: Phase/frequency detector for a phase-locked loop that samples on both rising and falling edges of a reference signal
- Patent Title (中): 用于在参考信号的上升沿和下降沿进行采样的锁相环的相位/频率检测器
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Application No.: US12204972Application Date: 2008-09-05
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Publication No.: US08401140B2Publication Date: 2013-03-19
- Inventor: Dejan Mijuskovic
- Applicant: Dejan Mijuskovic
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Dan D. Hill
- Main IPC: H03D3/24
- IPC: H03D3/24
Abstract:
A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the phase difference. The second phase detector is for detecting a phase difference at a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the phase difference. The combinational logic is coupled to receive the first difference signal and the second difference signal, and for preventing the second difference signal from being provided when the first difference signal is being provided.
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