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US08400846B2 Semiconductor integrated circuit with multi test 失效
半导体集成电路多测试

Semiconductor integrated circuit with multi test
Abstract:
A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.
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