Invention Grant
- Patent Title: Semiconductor integrated circuit with multi test
- Patent Title (中): 半导体集成电路多测试
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Application No.: US13280199Application Date: 2011-10-24
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Publication No.: US08400846B2Publication Date: 2013-03-19
- Inventor: Shin Ho Chu , Jong Won Lee
- Applicant: Shin Ho Chu , Jong Won Lee
- Applicant Address: KR
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR
- Agency: Baker & McKenzie LLP
- Priority: KR10-2007-0089489 20070904; KR10-2008-0013560 20080214
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/00 ; G11C8/00

Abstract:
A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.
Public/Granted literature
- US20120039137A1 SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST Public/Granted day:2012-02-16
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