Invention Grant
US08399314B2 p-FET with a strained nanowire channel and embedded SiGe source and drain stressors
有权
具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET
- Patent Title: p-FET with a strained nanowire channel and embedded SiGe source and drain stressors
- Patent Title (中): 具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET
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Application No.: US12731241Application Date: 2010-03-25
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Publication No.: US08399314B2Publication Date: 2013-03-19
- Inventor: Guy Cohen , Conal E. Murray , Michael J. Rooks
- Applicant: Guy Cohen , Conal E. Murray , Michael J. Rooks
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L29/267
- IPC: H01L29/267 ; H01L21/84

Abstract:
Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
Public/Granted literature
- US20110233522A1 p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors Public/Granted day:2011-09-29
Information query
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