Invention Grant
- Patent Title: Compiling apparatus
- Patent Title (中): 编译装置
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Application No.: US12048401Application Date: 2008-03-14
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Publication No.: US08392905B2Publication Date: 2013-03-05
- Inventor: Taketo Heishi , Shohei Michimoto , Yukio Iimura , Yasuhiro Yamamoto
- Applicant: Taketo Heishi , Shohei Michimoto , Yukio Iimura , Yasuhiro Yamamoto
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2007-082194 20070327; JP2008-009763 20080118
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/45

Abstract:
The present invention effectively utilizes auxiliary registers and provides a compiler system which secures error detectability when the auxiliary registers are shared for plural uses. The instruction definition resource configuring unit configures, as preparation for processing by the register assigning unit, respective resources such as a register to be defined or referred to by for each instruction in an intermediate code. The instruction definition resource configuring unit detects possibility of instructions each of which is to be decomposed into plural instructions. As for an instruction to be possibly decomposed, the instruction definition resource configuring unit configures a corresponding register in the intermediate code, assuming the corresponding register used for the decomposition to be defined and referred. The register assigning unit uses the register as a general register as far as a live range of the register used for the decomposition does not overlap.
Public/Granted literature
- US20080307403A1 COMPILING APPARATUS Public/Granted day:2008-12-11
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