Invention Grant
- Patent Title: Semiconductor device and layout design method for the same
- Patent Title (中): 半导体器件和布局设计方法相同
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Application No.: US13013442Application Date: 2011-01-25
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Publication No.: US08392856B2Publication Date: 2013-03-05
- Inventor: Akio Misaka , Yasuko Tabata , Hideyuki Arai , Takayuki Yamada
- Applicant: Akio Misaka , Yasuko Tabata , Hideyuki Arai , Takayuki Yamada
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2010-108285 20100510
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
Public/Granted literature
- US20110272815A1 SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME Public/Granted day:2011-11-10
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