A system including a processor, a first-in first-out (FIFO) module, and an arbiter module. The processor includes i) a processor core and ii) a memory. The FIFO module is configured to receive streaming data, output the streaming data to the memory of the processor, and selectively generate a control signal. The arbiter module is configured to adjust, based on the control signal, a priority in which at least one of the processor core and the FIFO module accesses the memory of the processor.