Invention Grant
- Patent Title: Systems and methods for coalescing memory accesses of parallel threads
- Patent Title (中): 并行线程内存访问的系统和方法
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Application No.: US12324751Application Date: 2008-11-26
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Publication No.: US08392669B1Publication Date: 2013-03-05
- Inventor: Lars Nyland , John R. Nickolls , Gentaro Hirota , Tanmoy Mandal
- Applicant: Lars Nyland , John R. Nickolls , Gentaro Hirota , Tanmoy Mandal
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G11C29/00

Abstract:
One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry.
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