Invention Grant
- Patent Title: Router design for 3D network-on-chip
- Patent Title (中): 路由器设计用于3D网络片上
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Application No.: US12751811Application Date: 2010-03-31
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Publication No.: US08391281B2Publication Date: 2013-03-05
- Inventor: Bipul C. Paul
- Applicant: Bipul C. Paul
- Applicant Address: US CA San Jose
- Assignee: Toshiba America Research, Inc.
- Current Assignee: Toshiba America Research, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Main IPC: H04L12/50
- IPC: H04L12/50

Abstract:
A network-on-chip router which includes an input buffer, an input controller connected to said input buffer, an arbiter connected to said input controller, a crossbar connected to said arbiter and said input buffer, and an output buffer connected to said crossbar. The network-on-chip router minimizes propagation time of data through the router by ensuring that the propagation delay of data through an input buffer is less than the combined propagation delay of data through an input controller and arbiter.
Public/Granted literature
- US20110243147A1 ROUTER DESIGN FOR 3D NETWORK-ON-CHIP Public/Granted day:2011-10-06
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