A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area.