Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.