A distortion compensation circuit capable of realizing highly accurate distortion compensation by updating a model even under a situation in which the appearance frequency of an input signal having a maximum value is low. A DPD processor 2 includes an inverse model estimation unit 22, which estimates an inverse model for a model expressing input-output characteristics of an HPA 6 based on an input signal S1 to the HPA 6 and an output signal S10 from the HPA 6, a distortion compensation unit 26, which compensates for distortion of the input-output characteristics by adding the inverse model to the input signal S1, and a sampling circuit 20, which samples the signals S2 and S10 in a predetermined time immediately before the sampling and inputs the signals S2 and S10 to the inverse model estimation unit 22. The inverse model estimation unit 22 updates the inverse model based on S2 and S10 input from the sampling circuit 20 regardless of whether the maximum value that the input signal S1 can take is included in a range sampled by the sampling circuit 20.