Invention Grant
- Patent Title: Delay configurable device and methods thereof
- Patent Title (中): 延迟可配置设备及其方法
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Application No.: US11435917Application Date: 2006-05-17
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Publication No.: US08390354B2Publication Date: 2013-03-05
- Inventor: Nitin Vig , Arnab K. Mitra
- Applicant: Nitin Vig , Arnab K. Mitra
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H03K3/289
- IPC: H03K3/289

Abstract:
A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.
Public/Granted literature
- US20070268053A1 Delay configurable device and methods thereof Public/Granted day:2007-11-22
Information query
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