Invention Grant
- Patent Title: Dense nanoscale logic circuitry
- Patent Title (中): 密集的纳米级逻辑电路
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Application No.: US13256234Application Date: 2009-04-30
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Publication No.: US08390323B2Publication Date: 2013-03-05
- Inventor: Dmitri Borisovich Strukov , Philip J. Kuekes
- Applicant: Dmitri Borisovich Strukov , Philip J. Kuekes
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- International Application: PCT/US2009/002680 WO 20090430
- International Announcement: WO2010/126468 WO 20101104
- Main IPC: H03K19/177
- IPC: H03K19/177

Abstract:
One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
Public/Granted literature
- US20120001653A1 Dense Nanoscale Logic Circuitry Public/Granted day:2012-01-05
Information query
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