Invention Grant
US08390318B2 Semiconductor device having calibration circuit for adjusting output impedance of output buffer circuit
有权
具有用于调整输出缓冲电路的输出阻抗的校准电路的半导体器件
- Patent Title: Semiconductor device having calibration circuit for adjusting output impedance of output buffer circuit
- Patent Title (中): 具有用于调整输出缓冲电路的输出阻抗的校准电路的半导体器件
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Application No.: US13401052Application Date: 2012-02-21
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Publication No.: US08390318B2Publication Date: 2013-03-05
- Inventor: Hideyuki Yokou , Takanori Eguchi , Manabu Ishimatsu
- Applicant: Hideyuki Yokou , Takanori Eguchi , Manabu Ishimatsu
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-035683 20110222
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.
Public/Granted literature
- US20120212254A1 SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT FOR ADJUSTING OUTPUT IMPEDANCE OF OUTPUT BUFFER CIRCUIT Public/Granted day:2012-08-23
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