Invention Grant
- Patent Title: Method and arrangement for reduced thermal stress between substrates
- Patent Title (中): 降低衬底之间热应力的方法和装置
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Application No.: US10678489Application Date: 2003-10-03
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Publication No.: US08390126B2Publication Date: 2013-03-05
- Inventor: Vahid Goudarzi , Juli A. Abdala , Gulten Goudarzi
- Applicant: Vahid Goudarzi , Juli A. Abdala , Gulten Goudarzi
- Applicant Address: US IL Libertyville
- Assignee: Motorola Mobility LLC
- Current Assignee: Motorola Mobility LLC
- Current Assignee Address: US IL Libertyville
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A module (20) can include a first substrate (12) comprised of a first material, at least a second substrate (22) comprised of at least a second material, selectively applied solder (14) of a first composition residing between the first substrate and at least the second substrate, and selectively applied solder (16) of at least a second composition residing between the first substrate and at least the second substrate. Preferably, no crack will exist in the module as a result of a reflow process of the solder due to the CTE mismatch between the first and second substrates. The different selectively applied solder compositions can have different melting points and can be solder balls, solder paste, solder preform or any other known form of solder.
Public/Granted literature
- US20050074955A1 Method and arrangement for reduced thermal stress between substrates Public/Granted day:2005-04-07
Information query
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