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US08390032B2 Depletion mode field effect transistor for ESD protection 有权
用于ESD保护的耗尽模式场效应晶体管

Depletion mode field effect transistor for ESD protection
Abstract:
A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.
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