Invention Grant
- Patent Title: Depletion mode field effect transistor for ESD protection
- Patent Title (中): 用于ESD保护的耗尽模式场效应晶体管
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Application No.: US13274103Application Date: 2011-10-14
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Publication No.: US08390032B2Publication Date: 2013-03-05
- Inventor: Yohichi Okumura , Josef Muenz
- Applicant: Yohichi Okumura , Josef Muenz
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A. R. Cooper; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: JP2006-257274 20060922
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L29/66

Abstract:
A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.
Public/Granted literature
- US20120032270A1 DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION Public/Granted day:2012-02-09
Information query
IPC分类: