Invention Grant
- Patent Title: Finishing method for a silicon on insulator substrate
- Patent Title (中): 硅绝缘体衬底的整理方法
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Application No.: US13257164Application Date: 2010-03-17
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Publication No.: US08389412B2Publication Date: 2013-03-05
- Inventor: Walter Schwarzenbach , Sébastien Kerdiles , Patrick Reynaud , Ludovic Ecarnot , Eric Neyret
- Applicant: Walter Schwarzenbach , Sébastien Kerdiles , Patrick Reynaud , Ludovic Ecarnot , Eric Neyret
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: Winston & Strawn LLP
- Priority: FR0951709 20090318
- International Application: PCT/EP2010/053460 WO 20100317
- International Announcement: WO2010/106101 WO 20100923
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
Public/Granted literature
- US20120021613A1 FINISHING METHOD FOR A SILICON ON INSULATOR SUBSTRATE Public/Granted day:2012-01-26
Information query
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