Invention Grant
- Patent Title: Semiconductor device and method for manufacturing the same in which variations are reduced and characteristics are improved
- Patent Title (中): 半导体器件及其制造方法,其中减小了变化并提高了特性
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Application No.: US13178248Application Date: 2011-07-07
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Publication No.: US08389350B2Publication Date: 2013-03-05
- Inventor: Akihito Sakakidani , Kiyotaka Imai
- Applicant: Akihito Sakakidani , Kiyotaka Imai
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2010-154846 20100707
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.
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