Invention Grant
- Patent Title: Foil-based method for packaging intergrated circuits
- Patent Title (中): 用于封装集成电路的基于箔的方法
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Application No.: US12858331Application Date: 2010-08-17
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Publication No.: US08389334B2Publication Date: 2013-03-05
- Inventor: Aninyda Poddar , Nghia T. Tu , Hau Nguyen
- Applicant: Aninyda Poddar , Nghia T. Tu , Hau Nguyen
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/31
- IPC: H01L23/31

Abstract:
One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method.
Public/Granted literature
- US20120043660A1 THIN FOIL SEMICONDUCTOR PACKAGE Public/Granted day:2012-02-23
Information query
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