Invention Grant
US08386981B1 Method and systems for implementing I/O rings and die area estimations
有权
实现I / O环和芯片面积估算的方法和系统
- Patent Title: Method and systems for implementing I/O rings and die area estimations
- Patent Title (中): 实现I / O环和芯片面积估算的方法和系统
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Application No.: US12978279Application Date: 2010-12-23
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Publication No.: US08386981B1Publication Date: 2013-02-26
- Inventor: Miles P. McGowan , Thaddeus Clay McCracken
- Applicant: Miles P. McGowan , Thaddeus Clay McCracken
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.
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