Invention Grant
- Patent Title: Semiconductor layout scanning method and system
- Patent Title (中): 半导体布局扫描方法和系统
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Application No.: US12593392Application Date: 2008-03-19
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Publication No.: US08386967B2Publication Date: 2013-02-26
- Inventor: Farid El Yahyaoui , Jozefus Godefridus Gerardus Pancratius Van Gisbergen , Jeroen Pieter Frank Willekens
- Applicant: Farid El Yahyaoui , Jozefus Godefridus Gerardus Pancratius Van Gisbergen , Jeroen Pieter Frank Willekens
- Applicant Address: IL Tirat Careml
- Assignee: Sagantec Israel Ltd.
- Current Assignee: Sagantec Israel Ltd.
- Current Assignee Address: IL Tirat Careml
- Agency: Nixon & Vanderhye PC
- Priority: EP07104863 20070326
- International Application: PCT/EP2008/053302 WO 20080319
- International Announcement: WO2008/116807 WO 20081002
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for scanning a semiconductor layout, the layout comprising objects with edges and corners, the method comprising identifying locally closest point pairs, identifying a proximity relation between two parallel edges where the parallel edges have at least one locally closest point pair in common and storing the proximity relation in a proximity relations table of a database together with a reference to the corresponding pair of edges. Locally closest point pairs are identified where the first edge and the second edge are not in contact with each other, a distance between the first point and the second point is the shortest distance between the first edge and the second edge, and a convex bounding area with the first point and the second point on its boundary contains no edge.
Public/Granted literature
- US20100185996A1 SEMICONDUCTOR LAYOUT SCANNING METHOD AND SYSTEM Public/Granted day:2010-07-22
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