Invention Grant
US08386859B2 On-chip non-volatile storage of a test-time profile for efficiency and performance control 有权
用于效率和性能控制的片上非易失性存储测试时间配置文件

On-chip non-volatile storage of a test-time profile for efficiency and performance control
Abstract:
Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.
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